Aim Project-concept Document Aim Scheduler Designs and Implementations

In this document, we discuss the philosophy, theory, and practice of scheduling computational processes on target hardware in the context of the Adaptive Image Manager (AIM) project. Emphasis is placed on (a) operational constraints, (b) highand low-level structure and functionality of technique, (c) algorithms and statistical analysis, and (d) design and performance analysis of the prototype and advanced scheduler implementations. The problem of realor near-real time computation in a reconfigurable heterogeneous computing system can be described in terms of a deterministic model based on analytical methods. In the perspective of real-time control, one first determines the flows of data and control that occur within and between the processes being modeled. Then, a hierarchical representation of these flows is derived, to yield an efficient representation of the process(es) to be computed on target hardware. Finally, the refined hierarchical representation is operated upon to determine (a) order of operation execution, (b) hardware to which a given operation should be mapped, and (c) estimated possibility (and, if feasible, probability) of hardware or software faults and failures. The AIM scheduler development effort has the following three phases: 1) Basic requirements and model of scheduling inherent in AIM process implementation; 2) Design and implementation of prototype AIM scheduler; and 3) Enhancement of scheduler to increase scope and depth of functionality as well as heterogeneity of target hardware considered. By accounting for hardware and software bandwidth as well as fault and failure rates estimated from built-in test procedures, it is possible to conform process execution to approximate performance constraints. Such results would help AIM designers and users implement given processing strategies to yield reduced overhead and increased process efficiency and robustness.